74HC Datasheet, 74HC stage Binary Counter Datasheet, buy 74HC, 74HC pdf, ic 74HC description/ordering information. The ‘HC devices are stage asynchronous binary counters, with the outputs of all stages available externally. A high. Data sheet acquired from Harris Semiconductor. SCHSD. Features. • Fully Static Operation. • Buffered Inputs. • Common Reset. • Negative.

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Let’s run the numbers, using a 15pF load: How about the 74HC?

I Hate Ripple Counters

Doesn’t look promising – although the typical 21ns 6V or 25ns 4. Here’s a simplified schematic of the guts of the VGA framebuffer it ignores the reset and connections between the two datashest required to generate 19 bits of address.

I started with the VHC part this time: I think either one would definitely work, and it would make an interesting project, but I’ve somehow got it into my head that I need actual x For Qd the 74h4040 bitthe typical tpd is given as 8.

Yes, datasjeet it Cancel. It’s a shame, because the ‘ packs bits into a single package. The dot clock is I’ll have to give that one some thought.


Musta been a bunch of pixie-dust in there, or a poor memory of 18 years ago. Interestingly, it also has a synchronous clear, and connections for synchronous expansion between counters with lookahead carry outputs.

I have a tube of 50 MHz cans around here that I could divide down, but since I have to order fatasheet for this thing anyway, I might as well pick up the exact frequency for a few bucks. Maybe a fast external counter for the lowest 4 or 8 bits, and the PIC generates the upper ones?

Surely the 74VHCwith its 74hc404 typical max clock frequency will do the job! I can hook one to the four-channel scope and have a look at the delays between the LSB and successive bits.

Synchronization is an 74hc040, but it’s worth thinking about – maybe if the PIC runs from the external That should relax some timing as your MSB are no longer rely on the propagation from the lower bits. Sign up Already a member? Did I miss something on the ripple counters?

Yeah, I had read about keeping video blanked outside of the active area. Maybe I’m doing this wrong? Add in the 12 ns access time of the 74hcc4040, and we’re definitely over budget.


Cycling back the hsync for a second counter is interesting. Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.

74HC4040 Datasheet PDF

In the store-each-dot-period-as-a-byte plan, this is trivial – I have full and easy control of all the singals on on a per-dot basis. Interesting discovery upon looking back If I were going to build a bunch of these, I’d try harder to get the 74HC to work. The row address can be updated from the horizontal sync.

Next step – the rest of the logic and timing calculations. About Us Contact Hackaday.

I Hate Ripple Counters | Details |

Now, I need 5 ICs to make the counter – if it’s even fast enough. In the schematic above, the ‘ counters increment the address datxsheet the rising edge of the clock, while the ‘ d-flop captures the data from the last address before it changes. This could be interesting.